In some analog/digital converters, an input signal is converted into a digital output code by a successive approximation technique. The converters operating on the basis of this technique are known as SAR converters (Successive Approximation Register). In the converters, a plurality of digital/analog conversion elements are provided which is suitably binary weighted and controlled by control logic. The digital/analog conversion elements are, for example, capacitor elements, resistor elements or current generators, generally with a terminal connected to a common node, or summing node connected to the input of a comparator by an operational amplifier, for example.
An example prior art converter is shown in FIG. 1, where in particular the basic layout of a SAR differential converter 1 with charge redistribution or capacitor arrays is illustrated. The plurality of digital/analog conversion elements, which together represent a local digital/analog converter 2, is arranged in one or more arrays (in the embodiment two arrays ARp and ARM are provided) with capacitance C0, . . . , CN-1 reciprocally binary-weighted according to powers of a unit capacitance, as indicated in the figure with the value C.
Furthermore, each of the two arrays ARP and ARM comprises a capacitance Cx, usually indicated with the term closing capacitance, and switching means or a switch Sx, . . . , SN-1 associated with the capacitances and controlled by binary signals output from a logic unit 3. The logic unit 3 is also known as a successive approximation register. The capacitance of each of the two arrays ARp and ARM has electrodes respectively connected to a first NSP and a second NSM common node, connected to respective inputs of a comparator 4.
The operation of the converter 1 is well known to those skilled in the art, and therefore, will not be further explained. In a first step in the converter 1, the differential analog input signal VINP−VINM is sampled using the arrays ARP and ARM of the capacitor elements. The capacitor elements are then used in the successive step to perform various attempts according to the logic of successive approximation. The sampled signal is compared to a reference voltage signal ΔVREF=VREFP−VREFM. The search strategy by successive approximation is carried out by the logic unit 3 on the basis of the binary signal CMPout output from the comparator 4. At the end of the search process, the logic unit outputs a digital code Dout resulting from the digital conversion of a sample of the differential analog input signal VINP−VINM.
A known design technique of converters using arrays of digital/analog conversion elements provides for the division of the arrays of digital/analog conversion elements into at least two array segments separated from each other by a serial capacitance. This includes a lower array segment and an upper array segment. Each segment comprises conversion elements weighted independently from those in the other segment. In the case of division of an array into two segments, the first segment is associated with the least significant bits (LSB) of the input digital code supplied by the logic unit. The second segment is associated with the most significant bits (MSB) of the input digital code.
The division makes it possible to optimize converter operation, facilitating control of the part performing the successive approximation search, and further enabling better utilization of the area effectively occupied by the array of conversion elements. In regards to these aspects, the existing SAR converters with a resolution greater than 6 or 7 bits have this type of topology. However, division into segments causes some problems, as illustrated below, related to control of the conversion element arrays. The problems are essentially of two types. They may arise jointly or separately, and they will be explained below without any particular order of importance.
The first type of problem will be described with reference to FIG. 2, where a converter 1 is schematically shown including arrays ARP, ARM of conversion elements divided into several segments. The converter is a particular embodiment of a 6 bits analog/digital converter produced according to the described in U.S. Pat. No. 6,600,437. As shown in FIG. 2, the analog/digital converter 1 comprises a digital/analog sub-converter 2 including a first array ARP, and a second array ARM of conversion elements in the form of a capacitor to which respective switching elements are associated.
Each of the two arrays ARP, ARM is divided into two conversion element segments by respective serial capacitance. The first array ARP is divided into a lower segment ARLP with 3 bits, and into an upper segment ARUP with 3 bits. The second array ARM is divided into a lower segment ARLM with 3 bits, and an upper segment ARUM also with 3 bits. In the embodiment, both the lower segments ARLP and ARLM are provided with a closing capacitance of unitary value.
The capacitances of the lower segment ARLP of the first array ARP have an electrode connected to a common node NSLP, while those of the upper segment ARUP of the first array have an electrode connected to a common node NSUP. Similarly, in the second array ARM, the capacitances of the lower segment ARLM have an electrode connected to the common node NSLM while the capacitances of the upper segment ARUM have an electrode connected to the common node NSUM. All the above-mentioned common nodes NSLP, NSUP, NSLM, NSUM represent summing nodes, since a sum of the analog signals is made at the nodes during operation of the converter 1.
During operation, in the input signal sampling step, the switches SWSAMP are closed and the summing nodes NSLP, NSUP, NSLM, NSUM are forced to the common mode voltage VCMCOMP imposed by the topology of the comparator 4. After the step, the switches SWSAMP, which are typically formed by transmission gates, are opened and consequently the summing nodes NSLP, NSUP, NSLM, NSUM remain floating. The subsequent switching of the capacitances of the arrays may need to be such that the potential of the summing nodes does not rise above the direct input voltage VDD of the converter and does not go below the ground voltage VGND.
If, on the contrary, one of the above-mentioned conditions takes place, the junctions would be biased directly towards the substrate of the switches SWSAMP. The result would be a loss current which would modify the charge stored in the capacitor arrays and compromise the accuracy of the conversion. This type of problem, also known as the dynamic range of summing nodes, afflicts converters with arrays of capacitance conversion elements divided into segments. In particular, this regards the summing nodes of the lower segments of the arrays of conversion elements. Potentially, the problem could also affect the summing nodes NSUP, NSUM of the upper segments ARUP, ARUM. But due to the development of the successive approximations, the problem has a much smaller or negligible effect on these nodes.
In another example, the problem of the dynamic range of the summing nodes is also present in a converter operating according to the method described in U.S. Pat. No. 6,720,903. The object of the patent is to offer an effective circuit approach to the problem of signal sampling with variable dynamic range in conversion structures comprising capacitor arrays. The technique makes it possible to control, with a discretization of 1 LSB, sampling of input signals with a dynamic range greater than or equal to the voltage reference value.
According to the method provided for in the above-mentioned U.S. patent, the input signal to be sampled is charged on a suitable fraction of the capacitor arrays. This includes charging the common mode voltage VCM on the remaining part where the signal to be converted is developed. In this way, it is possible to carry out scaling of the input signal without the presence of any external scaling circuit. Therefore, advantages in terms of a reduction in area and consumption are provided. However, it has been noted that a problem which can arise in a converter operating according to the above-mentioned U.S. patent concerns the possibility that, during the initial step of charging the input signal to be converted, the voltage of the summing nodes of the lower segments of the arrays reaches values outside the permitted dynamic range. Furthermore, after the initial sampling step, the problem of the dynamic range of the summing nodes can reappear during the various attempts at successive approximation. This happens in the converter illustrated in FIG. 2, for example.
A second type of problem related to the presence of arrays of conversion elements divided into segments arises when it is necessary to add an analog signal, such as an offset to the signal to be converted. To satisfy the requirement, the prior art uses auxiliary arrays, as in the differential analog/digital converter 1 schematically shown in FIG. 3. To sum an offset to the input signal to be converted, the illustrated converter which is identical to the converter shown in FIG. 2 is provided with two auxiliary arrays AUXP and AUXM scaled so as to control offset contributions of up to 4 LSB with discretization of a quarter of LSB.
During operation, in the input signal sampling step, the capacitances of the auxiliary arrays are connected to VCM and the summing nodes NSAP, NSAM of the auxiliary arrays AUXP and AUXM are forced to VCMCOMP, in the same way as the summing nodes of the two arrays ARP and ARM. Immediately after the sampling instant, the capacitances of one of the two auxiliary arrays AUXP and AUXM switch to VREFP or to VREFM, and those of the other auxiliary array switch dually to VREFM or to VREFP to introduce the desired offset.
According to another prior art approach, the auxiliary arrays AUXP and AUXM can be used, during an initial step to carry out a SAR conversion method intended to determine the voltage offset value of the converter, and subsequently to compensate the predetermined offset. Within the limits of the converter resolution, the offset can be cancelled with an accuracy determined by the scale of the auxiliary arrays AUXP and AUXM. Auxiliary arrays are used not only when it is necessary to sum an offset to the input signal, but also more generally, when it is necessary to sum an analog signal to the signal to be converted. For example, in the case where a dither needs to be introduced into the input signal, as is normal in the above-sampled converters (or sigma-delta converters).
The use of auxiliary arrays requires a significant increase in area occupation. Moreover, it should be considered that the auxiliary arrays AUXP and AUXM introduce further summing nodes NSAP, NSAM. For this reason, the design and layout of the local digital/analog converter 2 is particularly complex, especially if the first type of problem described above, i.e., the dynamic range of the summing nodes, is to be avoided.